Present complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. The extensive demand for dynamic random access memory circuits requires an optimal balance between minimum feature sizes and the inherent defect density of the process in order to maximize yield. The trend in dynamic random access memory design is to improve yield beyond that afforded by minimal defect density. This is accomplished by the addition of redundant elements that may be programmed to replace defective array elements and thereby improve yield.
Previous redundant circuits were unable to activate redundant elements and normal array elements with equal speed. This imposed a speed penalty on the entire dynamic random access memory, because its access time was characterized by the slowest element. In, U.S. Pat. No. 5,208,776, entitled PULSE GENERATION CIRCUIT, Nasu et al disclose a redundancy circuit in FIGS. 12-19 that is functionally similar to the circuit reproduced in FIG. 1 (prior art) for the purpose of illustration. Address buffers 16 and 18 are enabled by a clock signal CLK at terminal 14. They present a buffered address of N+1 bits to a programmable circuit 28, for example, in true and complementary form at terminals 20 and 24 and terminals 22 and 26 respectively. When the buffered address matches a stored internal address of the programmable circuit, the programmable circuit 28 produces a redundant address in which all bits are low on redundant address terminals 30-32. In response, NOR decoder 40 then produces a redundancy enable signal REN.sub.0 for enabling a redundant element. If any redundancy enable signal is high, NOR gate 56 produces a low enable signal EN to disable a defective array element. If no redundancy enable signal is produced, enable signal EN at terminal 58 goes high in response to a delayed complement of clock signal CLK at terminal 54.
The speed penalty of the circuit of FIG. 1 may be observed from the waveforms of FIG. 2 (prior art). Parasitic resistance and capacitance of interconnect at terminal 14 and buffered address terminals 20-26 vary significantly due to the remote physical placement of address buffers 16 and 18. Thus, a significant delay is noted between time T1, when clock signal CLK enables the address buffers, and time T2, when the last of redundant addresses RA.sub.0 -RA.sub.N is valid. At time T3 redundancy enable signal REN.sub.0 goes high after propagation delay through NOR decoder 40. Clock signal CLK must be inverted and delayed by element 48 until time T4 when all redundancy enable inputs at NOR gate 56 are valid to avoid false generation of an array element enable signal which would destroy data. This imposes a significant speed penalty, since a safe delay for element 48 under fast operating conditions may double under slow operating conditions where access time is specified. At time T5 a normal array element may be enabled. Thus, a significant speed penalty is noted from time T3 to time T5 for every normal array element access. Other circuit configurations may be used, but each contains a comparable speed penalty.